1. Field of the Invention
The present invention relates to a sense amplifier, and in particular to a power saving sense amplifier which significantly reduces power consumption in a programmable logic device.
2. Description of the Related Art
Programmable logic devices (PLDs) are well known in the art. A typical PLD architecture includes an array of function blocks interconnected via an interconnect matrix. Each function block includes an AND array which provides product terms to one of a series of macrocells in the function block. Each macrocell contains an OR gate into which product terms are gated, thereby providing a combinational function. This architecture is described in more detail in the 1994 Xilinx Programmable Logic Data Book on pages 3-5 to 3-8 which is incorporated by reference herein. To provide fast and accurate CMOS level signals to the OR gate, a plurality of sense amplifiers and associated bit lines are used as the AND array which outputs the product terms.
FIG. 1 shows such a known sense amplifier 100 having two enable lines ENA and ENA. Sense amplifier 100 is turned on or enabled by applying a logic 0 signal to line ENA, thereby turning off N-channel transistor 101, and a logic 1 signal to line ENA. Thus, the voltage level on a feedback line FB is established by a weak pull-up N-channel transistor 103 which is turned on by the logic 1 signal provided on line ENA and a strong pull-down N-channel transistor 104 which is controlled by the signal on bit line BL. The voltage provided to a feedback line FB controls the state of N-channel transistor 102, which operates in its linear range.
A weak P-channel transistor 105 and a strong N-channel transistor 102 provides a low trigger point at a bit line voltage on the order of 0.75 volts. If the voltage on bit line BL is high, transistor 104 turns more on, thereby pulling the voltage on feedback line FB lower. This lower voltage in turn causes transistor 102 to turn more off, thereby pulling up the voltage on bit line BL less and assisting the next movement on bit line BL (i.e. the voltage going low). Conversely, if the voltage on bit line BL is low, the voltage on feedback line FB is higher. This higher voltage in turn causes transistor 102 to turn more on, thereby pulling bit line BL to a higher voltage (via transistor 105 which serves as a current source, and operates in saturation mode).
Thus, the voltage on line ABL is controlled by transistor 102 in conjunction with bit line BL. Transistors 106 and 107 form a ratioed inverter, whereas transistors 108 and 109 form a second ratioed inverter. In response to the signal on bit line BL, the two ratioed inverters ensure that the output voltage provided on output line PT is at CMOS levels. Table 1 shows one example of logic 0 and logic 1 voltage values on the lines BL, FB, ABL, NBL, and PT.
TABLE 1 ______________________________________ Signal Logic 1 Logic 0 Difference ______________________________________ BL 0.769 v 0.746 v 0.023 v FB 1.77-1.88 v N/A N/A ABL 2.76 v 2.18 v 0.58 v NBL 0.491 v 3.33 v 2.84 v PT 4.4 v 0 v 4.4 v ______________________________________
Table 1 shows that a small swing in the voltage on bit line BL can produce a switch in the CMOS signal on output line PT.
Depending upon the states of EPROMs 121-1 through 121-n as controlled by word lines WL1 through WLn, the voltage on bit line BL is pulled lower or higher to indicate a logic 0 or logic 1 signal. If any of word lines WL1 through WLn is a logic 1 and assuming that EPROMS are erased, then the voltage on bit line BL is pulled lower to indicate a logic 0 signal. When biased on, EPROMs 121-1 through 121-n pull the voltage on bit line BL toward virtual ground VG. As shown in FIG. 1, virtual ground VG is separated from actual ground by transistor 111, which is controlled by a signal on line ABL.
Sense amplifier 100, however burns power constantly, irrespective of the voltage on bit line BL. Specifically, transistor 102 is always at least minimally on, thereby providing a current branch through conducting transistor 105, transistor 102, and transistor 112 (or additionally transistor 111 if at least one memory cell of EPROMs 121 is on). Note that because of the analog signal levels provided on lines ABL and NBL, transistors 106/107 and 108/109 also form current paths. Frequently, a plurality or all of the bit lines provide a low signal to their respective sense amplifiers. However, even in this state, considerable power is wasted in the PLD because of the current paths. Therefore, a need arises for a sense amplifier which minimizes power consumption.